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SLe2
Beginner
1,003 Views

Feasible Top Level Design of RSU, ASMI with Cyclone V via Ethernet?

Hello everyone!

I have a 5CEBA9F Cyclone V on a custom board with EPCQ128 and the goal is to write an application image via UDP Ethernet without using JTAG/USB Blaster. From a top level perspective, I will be utilizing a MATLAB script that will parse a POF file and send it byte addressable via UDP to the FPGA ethernet module. The FPGA will take the payload and insert into a FIFO (512 words with a flag for half full). There will be a check for sending an ACK back to the MATLAB GUI to only send another data packet if it received a valid packet and FIFO is not half-full since it's likely ASMI writing will be slower than the datastream coming in. A controller will be used to send this data over to ASMI 256 bytes per page write until it reaches the end of the file. Then RSU will trigger an update to read from ECPQ128 and load the application file.

 

Factory file will be at address 24-bit 0x000000 with incrementing LEDS to verify file loaded. This can be flashed serially.

Application will be further out (likely subsector 1024 0x400000) with flashing LEDS via UDP.

 

Is this a possible approach without utilizing NIOS II and QSYS? Thanks.

 

-Steve

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5 Replies
Nooraini_Y_Intel
Employee
84 Views

Hi SLe2,

 

Rather than using .pof file, you need to use .rpd file which contain the correct binary bitsream for AS configuration scheme with EPCQ128 device. You can refer to the following user guide on this:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altremote.pdf

 

It does not matter whether using NIOS II and QSYS or not. In theory, as long you can design your host (UDP Ethernet) to be able to interface and communicate with the ASMI + RSU IP, then it should work. There are no exact example design on your application using UDP Ethernet protocol however you may refer to the design store page where there are available RSU+ ASMI example design that you can use as reference:

https://fpgacloud.intel.com/devstore/platform/?acds_version=any

 

Regards,

Nooraini

 

SLe2
Beginner
84 Views

Thank you Nooraini for the input on utilizing RPD. The RPD contains 12MB with the header stripped off. Would I be sending the entire file byte addressed including padded FF's? If I recall, the ASMI block can only write 256 bytes via PAGE_SIZE followed by busy signal. I will look into a RSU+ASMI design example since I believe I was working with a RSU Cyclone V template (which may be the same design).

Another question.

Would there be an issue to have only a factory image and writing only to a factory image at address 0x000000 without an application image? In other words, is there a consequence of bricking an FPGA if the RPD file happens to be corrupted? Also, does the sectors have to be erased (set to '1's) before writing into Page 0?

Appreciate the timely response. Thanks

 

-Steve

Nooraini_Y_Intel
Employee
84 Views

Hi SLe2,

 

I don't think there is an option to write the entire .rpd file. FYI, there are few IPs that you can choose to use to perform erase, read and write .rpd file into the EPCQ128 device. You can check out each user guide on the operation protocol that you think will meet your requirement.

a) ASMI Parallel IP :

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altasmi_parallel.pdf

b) ASMI Parallel II IP :

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-asmi2.pdf

c) Generic Serial Flash Interface IP :

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf

 

There is no issue if you only store the factory image in the EPCQ128 device. As long as the .rpd file was written correctly into the EPCQ128, the AS configuration would still work on the Cyclone V device. However since there is only one factory image in the EPCQ128 device, the RSU will not work as there is no application image. If the .rpd file is corrupted, mostly AS configuration would fail but unlikely to brick Cyclone V.

 

In flash device architecture, before you can write any data, you need to perform erase first. You can refer to the following link for the explanation:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

 

Regards,

Nooraini

 

 

 

SLe2
Beginner
84 Views

I'll reclarify since you said there's no option to write the entire .rpd file. Correct me if I'm wrong, a user cannot write the RPD file in one go. My intentional design is to erase the corresponding sectors of interest and since I can only page write a maximum of 256 bytes, I will push into ASMI one-byte at a time until 256 bytes, then allow ASMI to write to EPCQ128 and monitor the busy signal, then continue the next 256 bytes and ensuring the next address is indexed properly. The last data packet will likely be less than 256 bytes so I would think it can be padded with FF. After everything is sent, have RSU reconfigure the FPGA and monitor any errors or LED feedback to ensure success of file. Is this method allowed for sending the complete RPD file to ASMI to configure the EPCQ128?

 

I may just leave a simple factory image with ASMI+RSU+UDP Ethernet enabled and focus on having an application image successfully stored to still utilize RSU. Since you brought up RSU wouldn't not work without an application image, if a factory image was programmed to EPCQ128 with only ASMI+UDP Ethernet, would I just need a controller to reset the FPGA via nCONFIG? Thanks again.

 

-Steve

 

Nooraini_Y_Intel
Employee
84 Views

Hi Sle2,

 

A user cannot write the RPD file in one go. This is correct, in any flash device you can send the data one-byte at a time. This is pretty much what ASMI IP feature offers. As mentioned previously, you can check from the ASMI IP user guide which write operation that fits to your requirement either a single-byte write or page-write operation:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altasmi_parallel.pdf

 

Typically users would user RSU IP to reconfigure the FPGA with multiple different images and have a factory image (that function as fail-safe image). There is known issue for Cyclone V, Arria V and Stratix V that cause the RSU IP won't work with just a single factory image. You can refer to this KDB link:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

 

If you just want to update and store a single image in the EPCQ128, then yes you need to be able to control the nCONFIG pin to trigger the reconfiguration. You need to find a way such as a controller to pulse the nCONFIG (high to low and return back to high).

 

Regards,

Nooraini

 

 

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