Finite State Machines and DSP

[Altera_Forum]

Hi everyone, 

 Im opening this topic because I have a question concerning the interaction between a DSP model and a Finite State Machine. I would need a Finite State Machine to drive my datapath fully designed with Advanced DSP blocksets. My question is with which tool do you advice to do that? At the beginning I was indecided between 'StateFlow' and the block 'State Machine', the problem is that the former requires a license while the latter belongs to the Basic DSP Blockset so it is not so straightforward to use.  So excluding State Flow is there some easy way to implement a FSM instead of mixing advanced and basic blocks of the DSP?  Thanks in advance

[Altera_Forum]

My suggestion, is just drop the tools and write the FSM in the language of your choice. (Verilog or VHDL). 

 You will have more control over the functionality, and a better understanding of the code that way.  My finding with DSP builder, is that it's a great way to get something up and running quickly, but in almost all the designs that I've looked at it with, it doesn't offer the flexibility the design requires. IE it will generate a really compact design, but it doesn't provide a method for a generic set that is programmable for coefficients (Or number of taps with-in reasonable limits).  Since the Filters used, seems to be one of the most contested parts of many of the designs, having the flexibility of programmability tends to make my customers happy.. (And has saved ASIC re-spins when they could just reprogram the coefficients to change the response.)

[Altera_Forum]

--- Quote Start ---  My suggestion, is just drop the tools and write the FSM in the language of your choice. (Verilog or VHDL).  You will have more control over the functionality, and a better understanding of the code that way.  My finding with DSP builder, is that it's a great way to get something up and running quickly, but in almost all the designs that I've looked at it with, it doesn't offer the flexibility the design requires. IE it will generate a really compact design, but it doesn't provide a method for a generic set that is programmable for coefficients (Or number of taps with-in reasonable limits).  Since the Filters used, seems to be one of the most contested parts of many of the designs, having the flexibility of programmability tends to make my customers happy.. (And has saved ASIC re-spins when they could just reprogram the coefficients to change the response.)  --- Quote End ---    And what about the testbench? Could I include a include the VHDL file in the Simulink model? I saw that only the Basic DSP blocks let do this...