Fitter error regarding the EMIF IP

[anonimcs]

Hi all,

I have a design on Quartus Prime Standard version 17.1. (I'm already considering an upgrade to 21.3 Pro after fixing this error, so please don't recommend this straightaway). In the design there are several Intel IPs including two external memory interfaces, one for HPS and one for the FPGA fabric. During the fitter stage, I get the following error. I'm following the recommended steps, generating HDL from the qsys file after I build the connections for my project and then run a full compilation on Quartus. I tried removing the generated directories and then re-generating HDL but didn't help. So far I couldn't find the source of this issue, so looking forward to your suggestions.

Kind regards

Info (332104): Reading SDC File: 'hps/altera_temp_sense_171/synth/altera_temp_sense.sdc'
Info (332104): Reading SDC File: 'hps_SOM01/altera_emif_arch_nf_171/synth/hps_SOM01_altera_emif_arch_nf_171_rwudowq.sdc'
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Critical Warning: get_entity_instances : Could not find any instances of entity hps_SOM01_altera_emif_arch_nf_171_rwudowq
Error: The auto-constraining script was not able to detect any instance for core < hps_SOM01_altera_emif_arch_nf_171_rwudowq >
Error: Make sure the core < hps_SOM01_altera_emif_arch_nf_171_rwudowq > is instantiated within another component (wrapper)
Error: and it's not the top-level for your project
Critical Warning (332008): Read_sdc failed due to errors in the SDC file
Warning (332060): Node: hps:i_hps|altera_reset_controller:rst_controller_004|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Latch hps:i_hps|sweep_gen:sweep_generator_0|s_phi_inc_cdc_in[31]~1 is being clocked by hps:i_hps|altera_reset_controller:rst_controller_004|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: i_hps|ddr4|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: i_hps|ddr4|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: i_hps|ddr4|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: i_hps|ddr4|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: i_hps|fpga_emif_ddr4|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: i_hps|fpga_emif_ddr4|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: i_hps|fpga_emif_ddr4|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: i_hps|fpga_emif_ddr4|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf  from: oe  to: o
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332152): The following assignments are ignored by the derive_clock_uncertainty command
Error: Quartus Prime Fitter was unsuccessful. 4 errors, 326 warnings
    Error: Peak virtual memory: 8620 megabytes
    Error: Processing ended: Thu Sep 26 16:35:45 2024
    Error: Elapsed time: 00:01:56
    Error: Total CPU time (on all processors): 00:03:23
Error (293001): Quartus Prime Full Compilation was unsuccessful. 5 errors, 1642 warnings

[sstrell]

What device is this?  What does your Platform Designer system look like?  EMIF parameterization?  HPS setup for EMIF?

More detail needed here.

[anonimcs]

Sorry for the lack of information.

• The target device is an Arria 10.
• The system can be described as: The system has 2 EMIF IPs, one for HPS and one for the FPGA fabric (the entities use the external memory for de-interleaving huge amounts of data). The HPS is used for setting some registers from a GUI, so the HPS is talking to an AXI to Avalon MM Bridge and that bridge reads/writes registers of the other entities in the fabric.
• EMIF parameterization: 1200 MHz memory clock, with HPS Early Release. HPS EMIF uses half clock rate of user logic, fabric uses Quarter. Not sure what else you'd like to learn here since there are quite a lot of parameters.

[sstrell]

Show your PD system with connections between the HPS and the EMIF IP.  Have you successfully manually generated the system in PD?

[anonimcs]

Hi,

Yes, the generation of HDL was done successfully. I attached some screenshots taken from the Platform Designer to this reply.

Thanks for helping out!

[AdzimZM_Intel]

Hello,

I'm Adzim, AE from Altera will assist you in this case.

Maybe you can refer to this KDB to resolve your issue?

https://www.intel.com/content/www/us/en/support/programmable/articles/000083063.html#:~:text=The%20following%20critical%20warnings%20may%20occur%20when%20a%20SystemVerilog%20or

Please let me know if it fixes your issue. Thanks

Regards,

Adzim

[AdzimZM_Intel]

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.