Floating point accumulator - feedback loops

[Altera_Forum]

Hello, 

 I am attempting to design a single precision floating point accumulator. DSPB reports that a latency of at least 9 clocks is needed in the accumulation loop to allow for the floating point addition logic. As a consequence the accumulator can only run at 1/9 x the clock rate. My design needs it to run at the full system clock rate.   I can think of several ways of solving this, e.g. by instantiating 9 accumulators (by vectoring the input signals) and running each at 1/9 the clock rate. In an RTL design I would use a counter to sequence the data to the accumulators.   However I am fairly new to DSPB and wondered if the tool will allow a smarter way of achieving this. My first thoughts were to use some from of decimation block on the data that feeds the accumulators, but I am trying to stick with the Advanced block set, which does not have these.   Any help will be greatly appreciated.   Thanks,   Terry.

[Altera_Forum]

If you really have to run at system clock rate, then you will need parallel accumulators.  

 Is there any reason you are using floating rather than fixed point? fixed point accumulators can complete in a single clock cycle (as can fixed point multipliers). You get huge performance increases with fixed point over floating.

[Altera_Forum]

Tricky, 

 I am afraid I have no choice but to use floating point due to the dynamic range of the signals in the design.   I realise that I will need parallel accumulators, I was hoping there was a clever way of making the tools schedule data to them (I have vectored the input signals and this seems to control the multiple instantiations).

[Altera_Forum]

the control logic will be up to you. All you should need is a counter and a mux.

[Altera_Forum]

Tricky, 

 that is exactly what I have done. I just wanted to check that I was not missing some capability of the tool that would look after this automatically (like it does for TDM).   Thanks for your help.