For Cyclone 10 is it acceptable to generate CLKUSR from a PLL?

[BAdam1]

We are using the Cyclone 10 PCIe Hard IP. Is it acceptable to generate the CLKUSR clock from a PLL in the same device? We are not concerned about the delay that will be caused.

[Rahul_S_Intel1]

better to use from the FPLL

[Rahul_S_Intel1]

I am also assuming you are using Cylcone 10 GX