GTS PMA/FEC Direct set-up

[K606]

I am looking through the GTS docs, and have noticed that there is a setup sequence:

In the generated /hwtest directory, this is all controlled via a set of .tcl scripts through Quartus system console.

My questions are

1: Where are the hex addresses defined from in the /src folder?

2: It seems this example is a standalone - excuse my ignorance, but is there a standard way to go about integrating this example into a larger project?

Thanks!

[ProFromDover_Altera · Accepted solution]

I'm not sure this question is posted into the proper forum, it seems more like an FPGA IP forum topic.

Where are the hex addresses defined from in the /src folder?

The example designs generated for the GTS IP generally connect one JTAG Avalon Master Bridge to the subordinate/slave interface of the IP core alone.  So the address map that the system console scripts are accessing are defined by the GTS IP core itself.  This is a rather complex core with multiple functions define a different base addresses within the IP core itself but you should be able to correlate the references that you see in the system-console scripts to the various register maps defined in the user guide.

Is there a standard way to go about integrating this example into a larger project?

This is a standalone design example that gets generated to evaluate the IP in this standalone configuration.  There is no standard way to integrate this example into a larger project.  Fundamentally, once you understand how the IP core operates in the mode that you're interested in using, you would then determine what makes sense from an implementation perspective to fit this functionality into your larger project.  But since there are many different applications that the GTS can be integrated into, there is no standard way to do this.  It's possible that you may find other system level example designs that would demonstrate a specific implementation of the GTS in that use case which may provide a better example of how it could be implemented in that specific use case.

[K606]

Thanks @ProFromDover_Altera 

Is it necessary to edit these AVMM registers in order to get a loopback running?

Or will the default loopback setting:

Suffice to get a loopback, along with this tx-rx serial setup:

...
assign gts_i_rx_serial_data = gts_o_tx_serial_data;
assign gts_i_rx_serial_data_n = gts_o_tx_serial_data_n;
...
qsys_top soc_inst (
...
.intel_directphy_gts_0_o_tx_serial_data_o_tx_serial_data         (gts_o_tx_serial_data),
.intel_directphy_gts_0_o_tx_serial_data_n_o_tx_serial_data_n     (gts_o_tx_serial_data_n),
.intel_directphy_gts_0_i_rx_serial_data_i_rx_serial_data         (gts_i_rx_serial_data),
.intel_directphy_gts_0_i_rx_serial_data_n_i_rx_serial_data_n     (gts_i_rx_serial_data_n),
...
);

Many thanks,

K

[ProFromDover_Altera]

Have you looked at section 6.12 of the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs?

It states:

• The example design runs an external loopback test by default, with the loopback_mode parameter set to 0.
  To perform an internal loopback test you must set the loopback_mode to 1 in the parameter.tcl file, located at: <design_example_dir>/hwtest/src/
• If needed, update the JTAG port ID by modifying the jtag_port_id parameter in the same file. The default value is 0.

[K606]

I am looking now to parameter.tcl file, it looks like this:

# (C) 2001-2025 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and other 
# software and tools, and its AMPP partner logic functions, and any output 
# files from any of the foregoing (including device programming or simulation 
# files), and any associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License Subscription 
# Agreement, Altera IP License Agreement, or other applicable 
# license agreement, including, without limitation, that your use is for the 
# sole purpose of programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the applicable 
# agreement for further details.


# (C) 2001-2024 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions and other 
# software and tools, and its AMPP partner logic functions, and any output 
# files from any of the foregoing (including device programming or simulation 
# files), and any associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License Subscription 
# Agreement, Intel FPGA IP License Agreement, or other applicable 
# license agreement, including, without limitation, that your use is for the 
# sole purpose of programming logic devices manufactured by Intel and sold by 
# Intel or its authorized distributors.  Please refer to the applicable 
# agreement for further details.


set LINK_MNG_SIDE_CPI_REGS(0)      0xA403C
set PHY_SIDE_CPI_REGS(0)           0xA4040
set LINK_MNG_SIDE_CPI_REGS(1)      0x1A403C
set PHY_SIDE_CPI_REGS(1)           0x1A4040
set LINK_MNG_SIDE_CPI_REGS(2)      0x2A403C
set PHY_SIDE_CPI_REGS(2)           0x2A4040
set LINK_MNG_SIDE_CPI_REGS(3)      0x3A403C
set PHY_SIDE_CPI_REGS(3)           0x3A4040

set LANE_ADDR                   0xA5000


set NUM_XCVR                    0x1
set SET_SILB(0)                 0x6A040
set SET_SILB(1)                 0x6A140
set SET_SILB(2)                 0x6A240
set SET_SILB(3)                 0x6A340
set RESET_SILB(0)               0x62040
set RESET_SILB(1)               0x62140
set RESET_SILB(2)               0x62240
set RESET_SILB(3)               0x62340

set SET_LANE(0)                 0x7A00F
set SET_LANE(1)                 0x7A10F
set SET_LANE(2)                 0x7A20F
set SET_LANE(3)                 0x7A30F
set RESET_LANE(0)               0x7200F
set RESET_LANE(1)               0x7210F
set RESET_LANE(2)               0x7220F
set RESET_LANE(3)               0x7230F

set SET_MODE(0)                 0xb1A003
set SET_MODE(1)                 0xb1A103
set SET_MODE(2)                 0xb1A203
set SET_MODE(3)                 0xb1A303
set RESET_MODE(0)               0xb12003
set RESET_MODE(1)               0xb12103
set RESET_MODE(2)               0xb12203
set RESET_MODE(3)               0xb12303


set DIS_SET_SILB(0)             0x0A040
set DIS_SET_SILB(1)             0x0A140
set DIS_SET_SILB(2)             0x0A240
set DIS_SET_SILB(3)             0x0A340
set DIS_RESET_SILB(0)           0x02040
set DIS_RESET_SILB(1)           0x02140
set DIS_RESET_SILB(2)           0x02240
set DIS_RESET_SILB(3)           0x02340



set DIS_SET_LANE(0)             0x0A00F
set DIS_SET_LANE(1)             0x0A10F
set DIS_SET_LANE(2)             0x0A20F
set DIS_SET_LANE(3)             0x0A30F
set DIS_RESET_LANE(0)           0x0200F
set DIS_RESET_LANE(1)           0x0210F
set DIS_RESET_LANE(2)           0x0220F
set DIS_RESET_LANE(3)           0x0230F


set DIS_SET_MODE(0)             0x00A003
set DIS_SET_MODE(1)             0x00A103
set DIS_SET_MODE(2)             0x00A203
set DIS_SET_MODE(3)             0x00A303
set DIS_RESET_MODE(0)           0x002003
set DIS_RESET_MODE(1)           0x002103
set DIS_RESET_MODE(2)           0x002203
set DIS_RESET_MODE(3)           0x002303




set DISABLE_DSP_ADAPT(0)        0x40A00C
set DISABLE_DSP_ADAPT(1)        0x40A10C
set DISABLE_DSP_ADAPT(2)        0x40A20C
set DISABLE_DSP_ADAPT(3)        0x40A30C


set SNF_MODE(0)                  0xA700C
set SNF_MODE(1)                  0xA7014
set SNF_MODE(2)                  0xA701C
set SNF_MODE(3)                  0xA7024

set RX_ADPAT(0)                  0xA7010
set RX_ADPAT(1)                  0xA7018
set RX_ADPAT(2)                  0xA7020
set RX_ADPAT(3)                  0xA7028

set ux_q_lane(0)                0x9781C
set ux_q_lane(1)                0x19781C
set ux_q_lane(2)                0x29781C
set ux_q_lane(3)                0x39781C

It seems there is not mentioned 'loopback_mode' or 'jtag_port_id'.

In section 6.6 I can see that the command sequence:

source main.tcl
set_jtag <number_of appropriate_JTAG_master>
run_test_silb

Should perform an internal serial loopback, however for me I am seeing this:

Hi yes I did see this - after compilation, you can see here that after performing these commands in section 6.6:

% run_test_silb
-----------------------------------------------------------
-----------------------------------------------------------
Link is not UP
-----------------------------------------------------------
Apply RX reset: 0x00000022 
Number of lanes : 1
 1.  0x6A040
 2. 0x0006a040
Polling Successfull Bit 15: 0x000001 , Bit 14: 0x000000
 1. 0x62040
 2. 0x00062040
Polling Successfull Bit 15: 0x000000 , Bit 14: 0x000000
Release reset: 0x00000000 
Number of lanes : 1
 Serial loopback on Lane# 0 is enabled 

PHY IP Setting	: 0x0002c067 
Scratch Register	: 0x00000000 
Soft Rst Crtl	: 0x00000000 
TX/RX/AVMM Ready	: 0x00000010 
TX PLL Locked	: 0x00000001 
CDR LTR & LTD	: 0x00000001 
RX ignore LTD	: 0x00000000
Alarm status	: 0x00000000
-----------------------------------
Value from issp reset probe is 0x45/0b1000101
--------------------------
 Test Fail : Check the Link Status 
--------------------------
--------------- SILB TEST DONE ---------------- 

Apply RX reset: 0x00000022 
Number of lanes : 1
 1.  0x0A040
 2. 0x0000a040
Polling Successfull Bit 15: 0x000001 , Bit 14: 0x000000
 1. 0x02040
 2. 0x00002040
Polling Successfull Bit 15: 0x000000 , Bit 14: 0x000000
Release reset: 0x00000000 
Number of lanes : 1
 Serial loopback on Lane# 0 is disabled 

Maybe you know of what do do?

Many thanks!

[paveetirrasrie_Intel]

Hello,

Good day.

I noticed you've marked Solved to the case. Kindly confirmed if the issue resolved at your end.

Regards,

Pavee

[paveetirrasrie_Intel]

Hello,

We didn't hear from you since last update and assumed your query have been answered since you've marked as solved. Hence, the thread has been closed. If you have a new question, feel free to open a new thread to get the support from Altera experts. 

Otherwise, the community users will continue to help you on this thread. 

Thank you.