Re: Gate level simulation in ModelSim with DSP Builder generated designs

Altera_Forum · ‎10-13-2009

I try to further verify my design in DSP-Builder by applying gate-level simulation in Altera-ModelSim. But some modules which have no problems in RTL simulation do not work in the port-synthesis and gate-level simulation. I will try to describe my problems and would be grateful if someone could give some hints about how to fix it.

For instance, I have setup a counter in my DSP-Builder and can run the Simulink and rtl simulation on ModelSim without any problems. And then I run the full compilation in Quartus II to generate the vho and sdf files for post-synthesis and gate-level simulation in ModelSim. To do so, I also compile the altera_primitives_component.vhd into the altera library directory in ModelSim, so that I can compile the vho file into the work library. But then I get some warning messages when I run the post-synthesis simulation:

# Time: 0 ps Iteration: 0 Region: /tb_adder/dut File: C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder.vho

# Time: 0 ps Iteration: 0 Region: /tb_adder/dut File: C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder.vho

# Time: 0 ps Iteration: 0 Region: /tb_adder/dut File: C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder.vho

# Time: 0 ps Iteration: 0 Region: /tb_adder/dut File: C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder.vho

# Time: 0 ps Iteration: 0 Region: /tb_adder/dut File: C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder.vho

And my counter output become "UUUUUU".

When I try to run a gate-level simulation by further taking the sdf file into the simulation. Then I get the following error messages: ( my counter out is 8 bit, I get error for each bit port, but some messages are omitted here due to their similarities)

...

# ** Warning: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).

My questions are:

What is my problem here, did I forget something?

It seems that modelsim have problem with "dffeas". But what is it?

How should I integrate my DSP-Builder design into my top-level design in Quartus II? Now I use the "export" option of the DSP-Builder Signal Compiler to export the vhdl files to my project and then instantiate my DSP-Builder design. But many modules seem not to be working in the post-synthesis or gate-level simulation , although everything is fine in rtl level simulation.

Many thanks for your helps!

Yang

Altera_Forum · ‎10-13-2009

you shouldn't have to compile any libraries when using ModelSim-AE.

i'm not sure what the problem is but i recommend trying to simulate using the NativeLink flow which usually does a good job setting up the simulation:

http://www.altera.com/literature/hb/qts/qts_qii53001.pdf

Altera_Forum · ‎10-14-2009

Well, the problem is, the automatically generated tcl files does not compile the altera_primitives_components.vhd into the altera library, which is needed for the compilation of the vho file. So I just added this step to get the thing work.

As far as I know, NativeLink is not so flexible as using ModelSim directly. And I could not image if something does not work in ModelSim-AE will work with NativeLink.

Or you could provide me more details about the advantages of using NativeLink? Thank you!

Altera_Forum · ‎10-14-2009

from my previous link:

--- Quote Start ---

In the ModelSim-Altera software, the pre-compiled libraries for both functional and gate-level simulations are available. You do not have to explicitly compile these library files before running the simulation directly.

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i agree that NativeLink is not as flexible as using ModelSim or writing your own simulation script, but i often use NativeLink to generate the initial .do file and edit it to taste so i don't have to do the tedious work. :)