Hi,Is there away to auto-generate the verilog code of a register set (control and status) for your IP. I mean, If you design an IP and u want to interface it with a system bus (e.g. avalon) so u need to have control and status registers set compatible with this bus. is there an auto way to just specify the required registers and the read/write/clear attributes of each one then the verilog code is generated?
There are tools to take a list of registers with attributes and write RTL, but I'm not aware of any that integrate directly with avalon or sopc builder.A site that surveys several such tools is http://www.garystringham.com/rdt.shtml (http://www.garystringham.com/rdt.shtml) One of the tools is my own csrGen, found at my site: http://asics.chuckbenz.com (http://asics.chuckbenz.com) I would love to publish some info on how to tie csrGen generated logic into sopc builder, but I have not worked on that yet. If anyone would like to help me, I'd be delighted. I have only done limited integration work with sopc builder, just creating an interface over to my own logic. \chuck