FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6614 Discussions

How to instantiate the DDR2 controller with ALTMEMPHY?

Altera_Forum
Honored Contributor II
‎10-18-2011 08:29 AM
1,098 Views

Hi, 

 

I am working on my first FPGA project with cyclone III. I want to know how to instantiate the codes generated with DDR2 controller with ALTEMEMPHY IP into my top file(Verilog hdl), can anyone show me an example? 

 

Please help!
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎10-20-2011 01:04 AM
364 Views

Please !!! 

 

I need your help . Any advice and guidance will be appreciated.
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.