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Altera_Forum
Honored Contributor I
‎10-18-2011 08:29 AM
761 Views

How to instantiate the DDR2 controller with ALTMEMPHY?

Hi, 

 

I am working on my first FPGA project with cyclone III. I want to know how to instantiate the codes generated with DDR2 controller with ALTEMEMPHY IP into my top file(Verilog hdl), can anyone show me an example? 

 

Please help!
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Altera_Forum
Honored Contributor I
‎10-20-2011 01:04 AM
27 Views

Please !!! 

 

I need your help . Any advice and guidance will be appreciated.
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For more complete information about compiler optimizations, see our Optimization Notice.