Hi,
I am working on my first FPGA project with cyclone III. I want to know how to instantiate the codes generated with DDR2 controller with ALTEMEMPHY IP into my top file(Verilog hdl), can anyone show me an example? Please help!Link Copied
Please !!!
I need your help . Any advice and guidance will be appreciated.For more complete information about compiler optimizations, see our Optimization Notice.