PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!
Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your
profile.
I am working on my first FPGA project with cyclone III. I want to know how to instantiate the codes generated with DDR2 controller with ALTEMEMPHY IP into my top file(Verilog hdl), can anyone show me an example? Please help!
