FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Getting started with startix-10 e-tile

yairs
Beginner
328 Views

Hi.

I am trying to build a 100ge test equipment using an existing board that have startix10-tx connected to an optical module qsfp28-sr4. I am using the E-Tile Hard IP for Ethernet from the Quartus prime Ip library.

I Have already established the ethernet and transceiver reconfiguration interface, so i can talk to the module.

I Haven't designed the client side (packet generator) yet. I want to verify that the IP is working first.

I have disabled auto neg and link training as otherwise, I am getting a design that is valid for 1 hour only, and RBF building fails. Do I need auto neg for optical connection?

Additionally, I have two questions:

1. I am having trouble measuring my reference clock (should be 156.25M). Is there a way to verify that it is correct?

2. Can anyone provide a simple sequence to get and verify the link up on the transceivers? 

 

Any help and tip will be very appreciated.

Thanks in advance

yair.

 

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Ash_R_Intel
Employee
151 Views

Hi,

You could try example designs first:

2.3. 100GE with Optional RS-FEC Design Example


Regards


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Ash_R_Intel
Employee
103 Views

Hi,

Were you able to try out the example designs?


Regards


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Ash_R_Intel
Employee
38 Views

As we did not get any further response from you, we are closing the case. However, it will be open for the community members to comment upon.


Regards


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