H-tile Hard IP for Ethernet Intel FPGA IP error

[3f28dsboek]

I generated a 100G H-tile Hard IP for Ethernet Intel FPGA IP,  but when I compile the project it fails

My device is Stratix 10 MX development board ( set_global_assignment -name DEVICE 1SM21BHU2F53E2VGS1) 

Can anyone help me? Thank you!

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_CR2_PMA_RX_BUF(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175001): The Fitter cannot place 1 HSSI_CR2_PMA_RX_BUF, which is within H-tile Hard IP for Ethernet Intel FPGA IP ex_100G_alt_ehipc2_1920_whg7r4i.
Info (14596): Information about the failing component(s):
Info (175028): The HSSI_CR2_PMA_RX_BUF name(s): av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[1].s10_xcvr_native_inst|s10_xcvr_native_phy|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_cr2_pma_rx_buf.inst_ct1_hssi_cr2_pma_rx_buf
Error (16234): No legal location could be found out of 96 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): There is no routing connectivity between source HSSI_CR2_PMA_CDR_PLL and the HSSI_CR2_PMA_RX_BUF
Info (175026): Source: HSSI_CR2_PMA_CDR_PLL av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[1].s10_xcvr_native_inst|s10_xcvr_native_phy|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_cr2_pma_cdr_pll.inst_ct1_hssi_cr2_pma_cdr_pll
Error (175022): The HSSI_CR2_PMA_CDR_PLL could not be placed in any location to satisfy its connectivity requirements
Error (175022): The HSSI_CR2_PMA_RX_BUF could not be placed in any location to satisfy its connectivity requirements
Info (175029): 96 locations affected
Info (175029): HSSICR2PMARXBUF_1T1C0
Info (175029): HSSICR2PMARXBUF_1T1C1
Info (175029): HSSICR2PMARXBUF_1T1C2
Info (175029): HSSICR2PMARXBUF_1T1C3
Info (175029): HSSICR2PMARXBUF_1T1C4
Info (175029): HSSICR2PMARXBUF_1T1C5
Info (175029): HSSICR2PMARXBUF_1T1D0
Info (175029): HSSICR2PMARXBUF_1T1D1
Info (175029): HSSICR2PMARXBUF_1T1D2
Info (175029): HSSICR2PMARXBUF_1T1D3
Info (175029): HSSICR2PMARXBUF_1T1D4
Info (175029): HSSICR2PMARXBUF_1T1D5
Info (175029): and 84 more locations not displayed
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 8 errors, 26 warnings
Error: Peak virtual memory: 12571 megabytes
Error: Processing ended: Mon Mar 21 01:36:04 2022
Error: Elapsed time: 00:02:09
Error: System process ID: 31615

[3f28dsboek]

I generated a 100G H-tile Hard IP for Ethernet Intel FPGA IP,  but when I compile the project it fails

My device is Stratix 10 MX development board ( set_global_assignment -name DEVICE 1SM21BHU2F53E2VGS1) 

Can anyone help me? Thank you!

[3f28dsboek · Accepted solution]

The error is because IP isn't correctly generated