HDMI TX IO PLL Reconfiguration

[Bin_Wang]

Hi,

  I am using C10 GX105YF780 + Quartus Pro 19.2 for HDMI TX.

Here I clone the reference design and tried outputting internal test pattern to a monitor.

I can measure there are signal running on the TX channels.

But the firmware for IO PLL reconfiguration register read back, before or after the reconfig process the values are always 0. 

You can see "read_reg0x90 .jpg" captured from SignalTap..

How do I debug this?

BRs,

Bin

[Bin_Wang]

Hi all,

  I did more investigation on the IOPLL reconfiguration process.

From SignalTap, I can noticed the IO PLL register write is always fine.

And after write the final write command, mgmt_waitrequest asserted.

The mgmt_waitrequest did not return to de-asserted automatically and the watch dog timer after 600ms triggers a reset to the reconfiguration IP, terminated the process and de-assert the mgmt_waitrequest.

You can see this in attached wd_reset.png.

The read back command following the reset, always get values "0".

This time I have a reference clock with 148.5MHz and I would like to get a 297MHz as pixel clock.

The output of the PLL remains in 148.5MHz without any change...

Following the document, I confirmed the pll_hdmi_reconfig ip was configured with proper setting.

Althoug the pll_locked and gxb_ready signals are asserted and signals can be measured on XCVR channels.

The downstream device was unable to recognize what was delivered.

Please help to debug this weir problem!

Thank you!

[Bin_Wang]

I just remove the wd_reset from the list and the mgmt_waitrequest stayed in asserted forever...

FYI!