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Altera_Forum
Honored Contributor I
762 Views

Help please - Unable to Compile 32K FFT

Hi all , please advise me on below... 

 

I am following the tutorial from Altera website on 32k FFT point Design.... 

 

I have configure the FFT megacore and then trying to compile it... 

 

but i got error as below... 

 

Error: Port "data_imag_in" does not exist in macrofunction "fft_small_bot" 

Error: Port "data_real_in" does not exist in macrofunction "fft_small_bot" 

Error: Port "exponent_out" does not exist in macrofunction "fft_small_bot" 

Error: Port "fft_imag_out" does not exist in macrofunction "fft_small_bot" 

Error: Port "fft_real_out" does not exist in macrofunction "fft_small_bot" 

Error: Port "inv_i" does not exist in macrofunction "fft_small_bot" 

Error: Port "master_sink_dav" does not exist in macrofunction "fft_small_bot" 

Error: Port "master_sink_ena" does not exist in macrofunction "fft_small_bot" 

Error: Port "master_sink_sop" does not exist in macrofunction "fft_small_bot" 

Error: Port "master_source_dav" does not exist in macrofunction "fft_small_bot" 

Error: Port "master_source_ena" does not exist in macrofunction "fft_small_bot" 

Error: Port "master_source_eop" does not exist in macrofunction "fft_small_bot" 

Error: Port "master_source_sop" does not exist in macrofunction "fft_small_bot" 

Error: Port "reset" does not exist in macrofunction "fft_small_bot" 

Error: Port "data_imag_in" does not exist in macrofunction "fft_small_top" 

Error: Port "data_real_in" does not exist in macrofunction "fft_small_top" 

Error: Port "exponent_out" does not exist in macrofunction "fft_small_top" 

Error: Port "fft_imag_out" does not exist in macrofunction "fft_small_top" 

Error: Port "fft_real_out" does not exist in macrofunction "fft_small_top" 

Error: Port "inv_i" does not exist in macrofunction "fft_small_top" 

Error: Port "master_sink_dav" does not exist in macrofunction "fft_small_top" 

Error: Port "master_sink_ena" does not exist in macrofunction "fft_small_top" 

Error: Port "master_sink_sop" does not exist in macrofunction "fft_small_top" 

Error: Port "master_source_dav" does not exist in macrofunction "fft_small_top" 

Error: Port "master_source_ena" does not exist in macrofunction "fft_small_top" 

Error: Port "master_source_eop" does not exist in macrofunction "fft_small_top" 

Error: Port "master_source_sop" does not exist in macrofunction "fft_small_top" 

Error: Port "reset" does not exist in macrofunction "fft_small_top" 

Warning: 4 hierarchies have connectivity warnings - see the Connectivity Checks report folder 

Error: Quartus II Analysis & Synthesis was unsuccessful. 28 errors, 8 warnings 

Error: Peak virtual memory: 309 megabytes 

Error: Processing ended: Thu Feb 24 16:28:59 2011 

Error: Elapsed time: 00:00:37 

Error: Total CPU time (on all processors): 00:00:33 

Error: Quartus II Full Compilation was unsuccessful. 30 errors, 8 warnings 

 

I have no idea why it is so... Please advise me... Many thanks ..
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1 Reply
Altera_Forum
Honored Contributor I
28 Views

Did you follow the steps suggested on the Altera website? 

 

FFT 32K Point Design Example v1.0.0 README File This readme file for the Fast Fourier Transform (FFT) 32K Point Design contains information about the design example posted on the Altera Support website: http://www.altera.com/support/examples/exm-index.html Ensure that you have read the information on the design example web page before using the example. This readme file contains the following sections: o Package Contents o Tool Requirements o Quartus II Compilation o ModelSim Simulation Models o MATLAB Models o Core Directory Names o Release History o Design Examples Disclaimer o Contacting Altera Package Contents ================ Fast Fourier Transform (FFT) 32K Point Design Example v1.0.0 Design files in the zip download include: &#65533; fft_32K.v - Top level design file implementing the 32-K point FFT &#65533; parse_fft_input.v - Reorders the input sample into even and odd samples to feed into the two smaller 16K point FFT blocks &#65533; fft_small.v - Wrapper file generated by the FFT IP MegaCore. The core is configured to implement transform length of 16K, and it uses the streaming I/O data flow structure. &#65533; combine_fft.v - Recombines the output of the individual 16K point FFT blocks using the appropriate twiddle factors &#65533; fft_32K_streaming_tb.v - Testbench for RTL simulation &#65533; fft_32K_streaming_vo_msim.tcl - TCL script to automate the RTL simulation process in ModelSim &#65533; fft_32K_tb.m - MATLAB model to verify the RTL simulation results Tool Requirements ================= This design example requires the following software package: o Quartus II 5.0 or later o FFT MegaCore v2.1.3 o ModelSim version 6.0 or later Please contact your local sales representative if you do not have one of these software tools. Quartus II Compilation ====================== To run the compilation for the Viterbi Decoder Node Synchronization project in Quartus II, perform the following steps: 1. Open Quartus II project: File -> Open Project -> ..\Quartus_II\fft_32K.qpf 2. Specify the FFT MegaCore Function user library: Assignments -> Settings -> Category (User Libraries) Browse to the <path>\fft-v2.1.3\lib in the Library name box. 3. Review FFT MegaCore parameters using IP Toolbench: Tools -> MegaWizard Plug-in Manager Select "Edit an existing custom megafunction variation" and choose the FFT IP block: ../source/fft_small.v You can review the parameters by clicking on the "Parameterize" button in IP Toolbench. 4. Regenerate the FFT MegaCore files by clicking on the "Generate" button in IP Toolbench. 5. You are ready to compile the design in Quartus II: Processing -> Start Compilation To get more details on the FFT IP MegaCore, refer to the FFT MegaCore Function User Guide located at: http://www.altera.com/literature/ug/ug_fft.pdf ModelSim Simulation Models ========================== In IP Toolbench, the option to generate Verilog/VHDL simulation model is enabled in the "Set Up Simulation" window. The steps to generate the simulation models from IP Toolbench are highlighted in the previous section: "Quartus II Compilation". We will be using the Verilog IP functional simulation model to verify the design in ModelSim. To run the functional simulation for the FFT 32K Point design using ModelSim, perform the following steps: 1. In ModelSim, change the directory to the ..\altera\design_example\FFT_32K\source directory: File -> Change Directory 2. Open the fft_32K_streaming_vo_msim.tcl file and update the path to the megacore_lib_dir setting to where the FFT IP is installed. 3. Source the TCL script file: Tools -> Execute Macro -> fft_32K_streaming_vo_msim.tcl The TCL script sets up the ModelSim project, compiles the appropriate libraries and design files, runs the simulation, and displays the result in the waveform editor. To get more details on the IP Functional Simulation Models, refer to the Altera white paper titled "Using IP Functional Simulation Models to Verify Your System Design White Paper" located at: http://www.altera.com/literature/wp/wp_simgen.pdf MATLAB Models ============= To verify the RTL simulation results are correct, you can compare them with the results from the provided MATLAB models found in the ..\altera\design_example\FFT_32K\MATLAB directory To run the MATLAB models, perform the following steps: 1. In MATLAB, change the directory to the ..\altera\design_example\FFT_32K\MATLAB directory 2. To generate the twiddle factors for the 32K point FFT (twiddle precision is set to 16 bits), type the following command at the MATLAB workspace: >> = gen_twiddle_factor(32768, 16); 3. To run the MATLAB model, type the following command in the MATLAB workspace: >> fft_32K_tb If the ModelSim RTL simulation results match the results from the MATLAB models, it displays the following message: "Simulation passes - Results Match". Otherwise, it displays the following error message: "Simulation fails - Results Mismatch". Core Directory Names ==================== The default directory for your design example design is c:\altera\design_examples\fft_32K, but you can specify an alternative directory.
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