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MDehp
Beginner
895 Views

Hi everyone, Is there a mapping between the JTAG interface and the TSE IP for setting registers? how could I use the register settings from the tcl script in my vhdl design?

I want to use 2 tse MAC's in my own design in HDL-author, but it seems somehow that the registers that I configure through the Avalon-MM are not set correctly or that the registers for the PHY are not set correctly through the MDIO interface. I can not simulate my whole design due to encrypted files. However I can use the generated testbench from Intel and simulate the register values that I a want to set in the MAC.

 

The reference design from Intel uses tcl scripts to configure the TSE module through a JTAG interface. But the register settings don't match with the registers from the datasheet of the TSE.

I am using the MAX 10 development kit with Dual Ethernet port and 2 PHY’s.

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3 Replies
BoonT_Intel
Moderator
13 Views

Hi,

Since you are using MAX 10 Dev kit, perhaps this example design is helpful for you.

https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/max-10-single-port-triple-speed-ethern...

 

 

MDehp
Beginner
13 Views

Yes, that example does work, but i want to add another TSE in the design and use 2 PHY's. But then i dont know how to configure the second PHY through the tcl script. Is there a datasheet of the 88E1111 Phy of the register spaces?

BoonT_Intel
Moderator
13 Views