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Altera_Forum
Honored Contributor I
717 Views

Hil

I have a pipeline fft model that I want to run on a Stratix III FPGA using HIL. I am attaching a screenshot of my models with and without HIL blocks and the HIL configuration. Now I have the HIL configured and programmed to the FPGA. When I run the simulations I see no output in the scope. Where am I going wrong here? The model without HIL shows me the correct output. 

https://www.alteraforum.com/forum/attachment.php?attachmentid=3505  

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=3506  

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=3507
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4 Replies
Altera_Forum
Honored Contributor I
29 Views

i read the forum quite often, please avoid PMs about new threads 

 

the first thing to check the the reset polarity between the original .mdl Clock block and the HIL settings
Altera_Forum
Honored Contributor I
29 Views

Thanks for the reply. It is working now.. And sorry abt the PM.. Will not do that again..

Altera_Forum
Honored Contributor I
29 Views

was it the reset polarity?

Altera_Forum
Honored Contributor I
29 Views

In the clock it was low while in the signal block and HIL config it was high. So changed the clock to high

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