How can I enable the SR-IOV of PCIe core in Stratix V FPGA
We are using the Stratix V :5SGXMA7H2F35C2 FPGA and trying to enable the SR-IOV feature of the PCIe hard IP.
I read the Stratix V Hard IP for PCI Express User Guide, but no information can be found to help us doing so. I also search it in Altera websit and no reference can be found to teach user using SR-IOV feature. It's really a confusion to us that no document talking about such an important feature on FPGA. Is there any way to get some help for it? Thanks.