FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5915 Discussions

How can I enable the SR-IOV of PCIe core in Stratix V FPGA

Honored Contributor II

We are using the Stratix V :5SGXMA7H2F35C2 FPGA and trying to enable the SR-IOV feature of the PCIe hard IP. 

I read the Stratix V Hard IP for PCI Express User Guide, but no information can be found to help us doing so. 

I also search it in Altera websit and no reference can be found to teach user using SR-IOV feature. 


It's really a confusion to us that no document talking about such an important feature on FPGA. 

Is there any way to get some help for it? Thanks.
0 Kudos
0 Replies