I designed a PCI Express ENDPOINT with CycloneIV GX FPGA and implemented it with hard IP (Gen1, x1, avalonST). This ENDPOINT connects to Atom X86cpu via PCIE. How do I make Hard ip cause a analogous
PCI-Serr signal, generate a fatal unrecoverable error to RC, and get an NMI interrupt, what should I do?
There is currently no configuration to create Fatal Error (FE) from Hard IP itself. To generate a FE, you could do it from RP side either using software or using a PCIe exerciser. Unfortunately, Intel-PSG solutions don't offer this capability for Cyclone V PCIe Hard IP. As for analogue PCIe error signal, I believe you are referring to Signal Detect circuit or receiver detection circuit. If yes, we currently also don't have a method to trigger error for this circuits. However, you could do it externally, by changing the AC coupling capacitor (either than 75-200nF range) to trigger Receiver detection circuit failure. As for NMI interrupt, Cyclone IV GX cannot handle it.