Community
cancel
Showing results for 
Search instead for 
Did you mean: 
VBotn
Beginner
2,075 Views

How do I access the Intel® 'Cyclone V GX' DDR3 hard memory controller 'Configuration and Status Interface'?

 Is it correct description in documentation (External Memory Interface Handbook Volume 3: Reference Material (Updated for Intel® Quartus® Prime Design Suite: 17.0)) about 'csr_clk' and 'Hard Controller Register Map' ?

0 Kudos
8 Replies
Deshi_Intel
Moderator
72 Views

Hi VBotn,

 

Yes, your understanding is correct.

 

Thanks.

 

Regards,

dlim

VBotn
Beginner
72 Views

Hi dlim,

 

I found in documentation (External Memory Interface Handbook Volume 3: Reference Material (Updated for Intel® Quartus® Prime Design Suite: 17.0)) that in the 'Hard memory controller'

signal 'csr_clk' is output clock, which is the same as 'afi_clk'.

 

 But in reality 'MegaWizard' create input signal 'csr_clk'. What are maximum and minimum frequency

for this input ?

 

Thanks.

Regards,

VBotn

Deshi_Intel
Moderator
72 Views

Hi VBotn,

 

I can see your confusion from EMIF handbook statement "This interface is clocked by csr_clk, which is the same as afi_clk, and is always synchronous relative to the main data slave interface.".

 

What this statement meant is simply both clock are sync to EMIF IP data interface and not saying both clock are operating with same frequency. I am sorry as the statement is misleading.

 

Yes, csr_clk is input clock source for EMIF IP config and status register interface. It's meant to be low speed control interface clock coming from FPGA core clock network. We don't really specific min/max clock spec for it but I would advise 100MHz clock as general guideline.

 

Thanks.

 

Regards,

dlim

VBotn
Beginner
72 Views

Hi dlim,

 

Thank you for information about 'csr_clk' .

Please give me explanation about bits in control register 'CFG_AUTO_PCH_ENABLE'(address 0x069)

in 'Hard Controller Register Map'. I didn't found in documentation (External Memory Interface

Handbook Volume 3: Reference Material (Updated for Intel® Quartus® Prime Design Suite: 17.0))

the descriptions of this bits.

 

Thanks.

Regards,

VBotn

Deshi_Intel
Moderator
72 Views

Hi Vbotn,

 

I can see you are interested with auto precharge feature but unfortunately auto-precharge is not really supported in hard memory controller. (refer to attached pic)

 

You can consider to use soft memory controller (normal FPGA memory controller) instead if you are interested with auto precharge feature.

 

Thanks.

 

Regards,

dlim

VBotn
Beginner
72 Views

Hi dlim,

 

Thank you for advice about soft memory controller but it is a bit slower than hard memory controller ...

I tried to search 'control register map' in hard memory controller with 'RTL Viewer' but only found 8 registers connected with calibration process.

It seems that we cannot change settings of hard memory controller controller with 'Configuration and Status Interface'.

 

Thanks.

Regards,

VBotn

Deshi_Intel
Moderator
72 Views

Hi VBotn,

 

I didn't check the register count in RTL viewer but to be honest "Configuration and Status Interface" is not a popular feature.

 

I am not sure the reason why you want to use it but you can test it out in simulation first if you really want to exercise this feature. Cyclone V FPGA is a legacy product with minimum support from Intel FPGA. Normally I would recommend customer to migrate to Arria 10 or Cyclone 10 FPGA instead.

 

Thanks.

 

Regards,

dlim

VBotn
Beginner
72 Views

Hi dlim,

 

Thanks for clarifying. I understood.

 

Thanks.

Regards,

VBotn

Reply