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FPGA Intellectual Property

Discussions

Anyone have experience with using frame buffer to implement 3:2 pull-down?

FFT IP Core 8.1

DDR SDRAM High Performance Controller - are lots of warnings normal?

Frame Buffer (sopc) Issues

FIR serial multichannel timing diagrams

DDR2 High Perfomance Mimic Path failing timing

ALT_PLLRECONFIG block busy signal problem

Two problems about FFT V9.1 IP core.

Question about FIR filter outputs

DSP Builder and Simulink!

HDL Import, License Problem

OpenCore problem

MegaCore Product ID list?

Avalon-MM master interface on Frame Buffer

VIP Clocked Video Input Seperate Sync Timing Tolerance

Featured Content

Tone Mapping Operator IP Malfunctioning

Unable to simulate DDR3 controller

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)