How do I configure an I/O BAR in Cyclone IV GX PCIe core?

[MS]

I'm using a Cyclone IV GX FPGA and take advantage of the contained PCIe hard IP. In order to get around a cache issue, I would like to configure an I/O BAR instead of a memory BAR. However, I cannot spot a possibility to configure this in the PCIe Compiler in Platform Designer (18.1).

• Does Cyclone IV GX support I/O BAR implementation?
• If yes, how can I configure that?

Thanks for your inputs.

[Nathan_R_Intel]

​Hie,

Cyclone IV GX does not support I/O BAR implementation. My apologies on this.

This is covered in our documentation (Pg37):

https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/ug/ug_pci_express.pdf

Regards,

Nathan

[MS]

Hi Nathan, Thanks for your answer. Reading the indicated section (p 37/370) I learned that I need to distinguish between IP generated by QSYS vs the IP Compiler. In the later one I/O BARs are accessible when choosing a legacy endpoint implementation instead of the native one. Best wishes, MS