Community
cancel
Showing results for 
Search instead for 
Did you mean: 
SrLam9
Novice
1,231 Views

How does the Remote Update IP work?

Hi am trying to implement the Remote update IP core into my Arria 10 system with an EPCQ512. I want to have an application and factory configuration to fall back on. I am configuring the Remote update IP via a short Verilog file that I wrote. It checks the Reconfiguration Trigger Conditions parameter in the register and either attempts to reconfigure if the value is 0 (it should be zero at POR) or it just loops and does nothing. I have the watchdog timer enabled and I am using the input clock to reset the timer.

 

Currently, I have a .jic loaded into the EPCQ512L at 0x20 and nothing loaded at the specified address for the application configuration. How I figured this would work is since the address I specified has an invalid configuration, it should just load the factory page. If I load a .sof to my device it seems to load into configuration that is loaded at 0x20. I check this by having different system IDs. However, when I convert .sof into a .jic and load it into the EPCQ, it never boots. I cannot seem to figure out why it is not booting because my assumption would be that it loads the factory configuration because there is no configuration at the specified address, then the Verilog would read the reconfiguration trigger condition and check that the trigger was probably the watchdog timeout.

 

Are there any examples of implementing this IP?

 

Am I missing something here or am I interpreting something incorrectly?

 

Thank you

0 Kudos
12 Replies
Nooraini_Y_Intel
Employee
200 Views

Hi SrLam9,

 

Did you set the correct the Arria 10 MSEL pins to Active Serial x1/x4? Did you set the configuration scheme Active Serial x1/x4 int he Quartus project design before compilation? Can you provide screen shot on the steps you did to setup the project design and generating the .sof to .jic file?

 

There is an existing Arria 10 RSU example from the user guide. Please refer to page 43:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altremote.pdf

 

Thank you.

 

Regards,

Nooraini

 

SrLam9
Novice
200 Views

HI NYusof,

 

Thank you for the response.

I have attached screen capture of the JIC settings that I am using as well as the device settings of the project.

I do not have steps for setting up the design project as my project is actually based off of an development board project.

 

Thank you

Nooraini_Y_Intel
Employee
200 Views

Hi SrLam9,

 

Thanks for the update. Did you check the nCONFIG, nSTATUS and CONF_DONE signal after power up? Have you try to only perform normal AS mode without using RSU IP in the design? Just use a simple project design without RSU IP and test the AS configuration from EPCQL512 if your design can be program into the Arria 10 device.

 

Thank you.

 

Regards,

Nooraini

 

SrLam9
Novice
200 Views

Hi,

On power up, I read the Reconfiguration Trigger Conditions register. If it is 0, then the system tries to reconfigure to the application mode by:

  1. Setting the watchdog value
  2. enabling the watchdog timer
  3. changing the configuration mode
  4. writing the application page address
  5. asserting the reconfig signal to start the reconfiguration

for the logic, if it is not 0, it goes into an idle state.

 

Thank you

 

Nooraini_Y_Intel
Employee
200 Views

Hi SrLam9,

 

Have you actually try the example design which is proven to be working with 2 images (1 factory and 1 application image)? Try to do this to understand RSU correct behaviour before try to perform the fall back testing (empty application image). This is to ensure that you are able to perform AS configuration successful.

 

To be honest, your statement here in the original thread is confusing:

"However, when I convert .sof into a .jic and load it into the EPCQ, it never boots."

 

Since you mentioned it never boots, this only tell me the AS configuration does not work. As mentioned before,  did you actually check the nCONFIG, nSTATUS and CONF_DONE signal after power up? Have you try to only perform normal AS mode without using RSU IP in the design? Just use a simple project design without RSU IP and test the AS configuration to see if your design can be program into the Arria 10 device or not.

 

Thank you.

 

Regards,

Nooraini

 

SrLam9
Novice
200 Views

Hi Nooraini,

 

The design example provided with my Development kit does in fact work, so there is something wrong with my Verilog.

 

Thank you for your help.

SrLam9
Novice
200 Views

Hi,

 

After checking my Verilog, I found that the my reset generator for the WDT was not generating a signal.

 

However, I still cannot load the application configuration. After tracing with signaltap, I found that the data out when reading the Reconfiguration Trigger conditions register is 0x1F. Is this an erroneous value or is it possible for all of these reconfiguration triggers to occur simultaneously? (I did not toggle nConfig). Is this a cause of trying to use SignalTap with an .sof and remote update IP?

 

Thank you

 

Nooraini_Y_Intel
Employee
200 Views

Hi,

 

To be honest, this does not make sense for the Reconfiguration Trigger conditions register to be showing 0x1F which indicate all the 5 type errors are occurring. Did you follow the steps in the example design to generate the .jic file (which contain at least 2 .sof files) and program in the EPCQL device?

 

Regards,

Nooraini

SrLam9
Novice
200 Views

Hi Nooraini,

 

I played around with my project a little more. I tried adjusting the reset because I thought that it may have been trying to access the register too early (however, I do check the busy signal so this should not be the case). I have attached an image of my signaltap trace. Data out from the IP is initially 0x00000000, but changes to 0x00000FFF, then 0x0000001F when the read is asserted. What could be causing this? The signaltap project is to trigger on power-up. Also ignore the RemoteUpdate:RU|reset signal, it was renamed and I never replaced it.

 

Thank you

Nooraini_Y_Intel
Employee
200 Views

Hi SrLam9,

 

The reset input port does need to be set to 0. Since this is an active high signal, asserting this signal high will reset the RSU IP core. From the Signal Tap screen shot it does not show what is the data parameter that you are trying to set.

 

Can you provide some screen shots of the Signal Tap showing each parameter being set/write (AnF bit, watchdog timer, application boot address) before triggering the reconfig port for use to check the steps? Did you strobe/set the reconfig input to high at least for 250ns? This is the minimum require to set reconfiguration input of the RSU IP core high in order to start the reconfiguration.

 

Regards,

Nooraini

 

 

 

 

SrLam9
Novice
200 Views

Hi Nooraini,

 

Sorry about the screenshot, I forgot to explain that the Signal Tap only shows reading parameter 000 (reconfiguration trigger register). It does not show writing the parameters. As you explained, the first step is to check this register. This is where my problem lies. I am expecting to read 0 on PoR, but instead I am reading 0x1f.

As for providing screen shots for the signal tap for the reconfiguration, states 5'b00100 to 5'b01100 are for setting the reconfiguration application boot, wdt, and AnF bit, but Since I read a 0x1f from the reconfiguration trigger register it goes to 5'b11111 and does nothing there.

 

The reset_sequencer_0_reset_out0_reset is the reset going into the remote update ip block in Platform Designer.

 

Is there something wrong with my parameter read? It is similar to the example waveform given in the Remote Update IP Core User Guide, but I wait for the Busy signal to deassert before deasserting read_param whereas the example only asserts read_param for one clock cycle.

 

Thank you.

Nooraini_Y_Intel
Employee
200 Views

Hi SrLam9,

 

I have attached an example project design I just tested today on Arria 10 dev kit which works. You can refer to the rsu_cb.vhd which I wrote the parameters to read reconfiguration status register and write the AnF, disable watchdog timer and application image boot address. After power up the board (of course EPCQL was programmed with a .jic before), when I check using SignalTap to read the reconfiguration status register, I can observe the data_out[31..0] show 00000. You can try to check the rsu_cb.vhd and compare with yours.

 

Regards,

Nooraini

Reply