FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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How to adjust Video Output IP?


With Platform Designer for Terasic SoCKit board I made simple chain: Test Pattern Generator - Frame Buffer with DDR3 Memory - Clocked Video Output. Set resolution 1024 * 768 and to CVO enter parameters from VESA Timing Standart for such resolution. The display is empty. With oscilloscope I see non stable vertical synchronization. I have the same for another resolution. How to adjust CVO right way?

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Hi Serge, May I know what do you mean by display empty ? Can you elaborate further ? Just to confirm you are using clock video output (CVO) IP and not CVO II IP, right ? For the CVO IP, we don't have the preset for 720p but there should be preset for 1080p. You can cross check the setting with 1080p preset and if possible test it with 1080p. The other thing is normally we would connect CVO to another video interface IP like HDMI, SDI, Display Port or DVI. Have you isolated the display empty issue is contains in CVO IP and not on video interface IP ? Typically I would suggest to debug from video interface IP first, once it's proven working on monitor then only you slowly add in more design like CVO, frame buffer and DDR3. Thanks. Regards, dlim
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