I want to work on some specific addressing shceme as mentioned in https://www.repo.uni-hannover.de/bitstream/handle/123456789/9978/Dissertation_Meinl.pdf?sequence=3&i... (Figure 3.14)
To do that first I need to know the address remapping scheme from DDR3 to HPS and vice versa.
Right now i am working with ARRIA 10 SOC where as HPS is connected to emif as follows mentioned in our problem statement attachment below.
In online I found this link to know address mapping.
My question is as follows:
1. But how can i find or calculate for my memory that i used and for the configuration of command address that i used.
2. I found some source code in Verilog in a NIOS project about this address conversion in DummyAddressRemappingDDR3.v , according to that when i calculate for my arria 10 with hps connected to it, i get
ch = cmd;
row[15:0] = cmd[26:11];
bank[2:0] = cmd[10:8];
col[9:0] cmd[7:0] & "00";
But, here what happens to the cmd_address from [31:28], I suspect the above calculation i got is correct or not, can anyone clarify please.
some more questions:
The EMIF for HPS controller of the Arria 10 is connected to two SDRAM DDR3 modules. Both modules are connected to the same address and command bus. Only the data bus is combined to a 32-bit data bus. The Intel External Memory controller (EMIF) handbook describes the format of the Chip-Row-Bank-Col Bank interleaving on the address bus. This format is related to an 8-bit (Byte) formatted address bus. With this memory setup, is a word (32-bit) formatted address bus connected. Due to the fact that the EMIF for HPS is assigned to an ARM AXI bus and the ARM AXI bus uses a Byte address format is it necessary to convert a 32-bit (word) address format to an 8-bit (byte) address format. This will be automatically done. The question is how is the address format of Chip-Row-Bank-Col Bank changed to achieve this? Is this explanation correct for this setup?
Link to the EMIF Handbook: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.p...
Communicated via IPS:
The decoding table is attached and the maximum address is 0x3FFF FFFF. User shouldn't writing above this maximum address limit.
Since the end goal is to improve DDR3 performance throughput, and multiple method of changing data pattern address access has been done but still doesn't help, then the only hard way left is to increase DDR3 operating frequency.
However, the board design also must be able to handle higher frequency operation.