09-18-2019 04:58 PM
Is it possible to design and optimize an IP in Verilog and create a function for it that can be called from HLS?
A simple example of such scenario would be as follows:
- Design and optimize an FIR filter in Verilog.
- Create a function for the design in HLS.
- Write a nested `for` loop in HLS that calls the function associated with the filter.