I have set up a design with two TSE MAC's, the design already works in simulation.
Now I want to test the design on my MAX10 FPGA, but I can't figure out how to connect the second TSE MAC to the PLL clock. For the first TSE MAC I have used the "AN647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design" which works correctly.
I geuss I can use 1 PLL clock for both TSE MAC's ?
There are also 2 clk_ctrl instances in the reference design can I use these also for the second TSE MAC?
Any help is appreciated
Thanks for your reply.
I have another question concerning the MDIO interface.
Do you know if I could leave out the MDIO interface of both TSE MAC's in RGMII mode?
Or do I need to configure the PHY registers through the MDIO interface. (enable/disbale auto-negotiation?)
For now I have disabled the MDIO option for both MAC, but data transfer between the two MAC's isn't realized yet.
My FPGA uses 2x the 88E1111 PHY chip. Is it a must that I configure the MDIO registers, or are they configured automatically if I turn off both MDIO of the TSE IP?
Because I can't find the register mapping of the PHY chip.