- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I have generated a instance of ALT2GXB Can anyboy explain where to connect this signals??? fixedclk -- --The user must provide a 125 MHz input clock signal for the fixedclk port. rx_cruclk --Clock input from the PLD core. Connects to the clock reco very unit (CRU). I want to use this Megacore for using a 16 Bit PCIe PIPE within the FPGALink Copied
0 Replies
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page