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I am using Stratix4 hardip in pcie gen1 x4 configuration. The hard IP has PCI bar register configured for 512K memory space. The Root complex is sending out the memory read request (non-posted) to the Stratix4 FPGA end point with valid address (that belongs to 512K memory block). The end point sends a request to the appropriate device behind it. But that device only supports smaller chunk of that 512K memory block. Thus it does not respond with data to the cycle eventhough it belongs to its memory range. Is it OK to send out completer abort TLP back to the root complex in such a situation? If not how to gracefully terminate such a cycle?
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Okay, that one is old but easy to answer. From PCIe:
--- Quote Start --- If the Request is not a Message, and is a supported Type, specific implementations may be optimized based on a defined programming model which ensures that certain types of (otherwise legal) Requests will never occur. Such implementations may take advantage of the following rule: – If the Request violates the programming model of the device Function, the Function may optionally treat the Request as a Completer Abort, instead of handling the Request normally • If the Request is treated as a Completer Abort, this is a reported error associated with the Function (see Section 6.2) • If the Request requires Completion, a Completion Status of CA is returned (see Section 2.2.9) --- Quote End --- So, in short: You can treat the device’s restrictions as a limited programming model, and violating that is allowed to be responded by a Completer Abort (CA).- 新着としてマーク
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I did first try sending out completer abort TLP in such a case but the BFM (generated Megawaizard) hung up on it so I could not gracefully terminate the cycle. May be I did not send out right bits for completer abort.
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Remember: A Completion with a status other than Completer Success must be a Completion without data, and you must take care to properly set the byte length and lowest-significant byte address to free all allocated resources in the requester.
