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Altera_Forum
Honored Contributor I
863 Views

How to implement a FIR filter with the ALTSHIFT_TAPS megafunction

Good day, 

 

I am trying to implement an FIR that will have 128 taps of 21 bits each tap. 

 

I am trying to do this with the ALTSHIFT_TAPS megafunction. However, I am confused with the TAP_DISTANCE parameter. It seems to me that in order to make the design work I need to leave many empty spaces in the shift register, which would be quite inefficient. 

 

I understand the ALTSHIFT_TAPS megafunction was designed specifically for implementing very long FIRs. 

 

I have searched for Altera documents that may illustrate how to do this. The only one related to this megafunction is its actual user's guide, which does not include any examples (or at least I have not found them). 

 

Has anyone implemented an FIR with the ALTSHIFT_TAPS? I would really like to see an example. 

 

Thank you 

 

Jesus Carmona
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7 Replies
Altera_Forum
Honored Contributor I
56 Views

I used alt shift taps for FIR. The minimum distance between taps was 3 and what I did was to run the shift 3 times faster than sample rate thus tap distance was in effect reduced to 1.

Altera_Forum
Honored Contributor I
56 Views

Kaz, 

 

Thanks for the reply. Running the clock faster means that I will need to leave empty spaces in the shift register (i.e. if the tab distance is 3, then I enter my coefficients each one spaced with 2 zeros). Am I right?  

 

My filters are very long and I need to be careful with the resources of the FGPA. 

 

I have done more work on this, but apparently there is no free lunch. Either i leave empty spaces on the shift register or I need to use a lot of memory to store partial sums of the convolution process.
Altera_Forum
Honored Contributor I
56 Views

ALTSHIFT_TAPS is based on FPGA internal RAM. I suggest to think a bit about the principle restrictions of RAM based FIR designs. Basically, they can't read more than two locations per clock cycle for a single RAM block (using the dual port feature). Implementing fast shift registers with many taps means using many RAM blocks, that are only partly populated. You'll fastly run out of RAM resources this way. 

 

The Altera FIR MegaFunction is a good example how different storage options, both for data and coefficients can be chosen depending on the filter data rate. Even if you want to implement your own FIR design, reviewing the structures suggested by the FIR compiler can be quite instructive.
Altera_Forum
Honored Contributor I
56 Views

The idea is to save registers when you have a long filter plenty of ram to spare. Losing few ram locations is not an issue then and use of ram is highly recommended for speed as well. 

 

As regard shift and what you call "empty locations" you don't insert zeros. there are no empty locations but only the data is shifted through.  

 

In the case of FIR you need to tap each and every location. So if you set shift at tap distance of 3 and run at 3 x Fs then each tap will appear every three fast clocks i.e every Fs clock. 

 

edit: 

I should add that you enter your data into the shift at data rate but you shift it in at 3 times faster so you don't need to worry about inserting zeros.
Altera_Forum
Honored Contributor I
56 Views

To understand possible restrictions, it would be good to hear about the intended FIR sampling frequency. 

 

Regarding ALTSHIFT_TAP, of course it's possible to clock the RAM at triple Fs, but I think it's more straightforward, to implement a RAM based shifter according to your needs directly. Particularly, ALTSHIFT_TAPS isn't able to multiplex RAM accesses according to the Fclk to Fs ratio.
Altera_Forum
Honored Contributor I
56 Views

using alt-shift is atraighforward and does not need any muxing... 

all you need is a clock at 3xFs in phase then pass your data on Fs and read taps on Fs but let shift run at 3Fs.
Altera_Forum
Honored Contributor I
56 Views

 

--- Quote Start ---  

using alt-shift is atraighforward and does not need any muxing... 

--- Quote End ---  

 

I didn't say it's needed. I say, it can be interesting to multiplex the RAM (in time) if Fs allows it. I was thinking of the said 128 taps of 21 bits requirement.
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