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Qsys Pci Express HIP Avalon MM interface

Honored Contributor II

I'm using Quartus 11.0sp1 to generate the Hard IP pci express core. The avalon MM interface does not have a separate read byte enable, burstcount and address. In my Quartus 9.0 SOPC builder the DMA bridge contained separate read and write interfaces. Can I still do simultaneous read and write bursts as with the soft IP in Q9.0 ?

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