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How to improve timing in FIR Compiler II?

Altera_Forum
Honored Contributor II
‎04-27-2017 01:27 PM
1,223 Views

Hello @all, 

 

can anyone tell me how I can improve the timing with a filter generated by the FIRII. 

The top failing path has a slack of -820ps. 

If I locate the path in the Technology Map Viewer I see, that there need to be added some pipeline registers: 

https://alteraforum.com/forum/attachment.php?attachmentid=13599&stc=1  

 

Especially the registers at the input of the DSP Blocks are not used: 

https://alteraforum.com/forum/attachment.php?attachmentid=13600&stc=1  

 

I tried the Speed Grade Options Slow, Medium and Fast in Implementation Options. But there was no real difference. 

 

Target Device is Arria10 10AS066H3F34I2SG
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Altera_Forum
Honored Contributor II
‎10-19-2017 09:07 AM
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Hi Kippis,  

 

There is nothing much to optimize with the generated code. Your design may consist of (18+18) x 19 structure. If this is the case, you may try to increase the coefficient bit width to 20 or reducing the bit width to 18 and confirm whether the input registers are able to pack. This can help to determine whether the problem is due to the Quartus Synthesis.  

 

Best Regards, 

Terence 

 

(This message was posted on behalf of Intel Corporation)
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