FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6463 Discussions

How to infer systolic FIR mode DSP block in Arria V

Altera_Forum
Honored Contributor II
898 Views

Hi, 

 

Do someone know good ways to infer systolic FIR mode DSP block in Arria V? 

I develop the code attached, but it doesn't fit into one DSP block. 

I need the block to implement complex FIR filter. 

 

Regards,
0 Kudos
0 Replies
Reply