How to map TX Avalon-MM slave interface into PC virtual memory?

[EPino]

Hi,

I'd like to map TXS port to virtual memory but I am having a hard time understandig how to do that.

For example, in order to map BAR0 to virtual memory all I have to do is access the configuration space and get the BAR0 physical address then call something like ioremap, if using Linux. 

Is there a similar way to get the TXS port physical memory address?

Device: Cyclone IV GX

Best Regards,

Eduardo

[SengKok_L_Intel]

Hi,

BAR0 is AVMM master port, this is for host to access the endpoint (Host -> FPGA), where host issue read/write command, and FPGA response on it.

The TXS port is AVMM slave, this is for End point to access host (FPGA -> Host) where endpoint issue memory read/write command, and host response on it. The address width of the TXS depends on the setting of the size of address Page.

Regards -SK

[EPino]

Got it!

So the problem is: How do I know where in host memory will TXS write to?

Should I map host memory into the FPGA?

Regards,

Eduardo

[SengKok_L_Intel]

You have to map it to the host memory, and it depends where did you wanted to read/write from the system memory. This interface can access up to 4Gb of size.

Regards -SK

[EPino]

Ok, but that is the point of the original question. To map TXS to host memory i'll need a physicial memory address (that points to TXS base address), so that I can assign a virtual memory address to it, correct?

How can the host get that physical memory address? From the configuration space? Should I connect TXS to a BAR in Qsys?

Kind Regards,

Eduardo

[SengKok_L_Intel · Accepted solution]

Hi Eduardo,

No, the TXS port should connect to your application interface NOT BAR.

If the read/write request is initiated from your application via TXS port to the host, and then the host will be responding to those requests accordingly.

The size of the host system memory can be 32 bits (2 ^32) or maybe 64 bits (2^64), you will need to confirm it from your host system.

It depends on which locations of the system memory that you would like to read/write from FPGA. In the IP GUI, there is an address translator table for you to fill in, and this is up to the user to decide where the system memory that their design need to access.

Regards -SK 

[EPino]

Got it!

thanks!

[SengKok_L_Intel]

I will set this forum case to close-pending for now. The status will remain in this state for 20 calendar days, simply post a note in this forum and it will be reopened for further investigation.

Regards -SK