How to measure bus utilization in hardware

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

How to measure bus utilization in hardware

888 Views

Hi All,

I have an SOPC builder project (using the Video Processing suite) working in silicon.

I would like an indicator of "how much bus bandwidth" is being used at various points wired out to a GPIO so I can see how much capacity I have left for real (I have done the spreadsheets to predict bandwidth etc.)

Its a video project, so simulating takes a long long time (need to run for lots of ms).

I am using the Avalon-MM bus, wondered if there is a "recommended way" to wire out the bus_req/bus_wait sort of signals to a GPIO without going in and editing the sopc VHDL output each time.

Any pointers?

Thanks

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.