How to properly constrain the PFL for STA

[Knug]

Hi @JohnT_Intel

FPGA_dclk output of the PFL (Parallel Flash Loader). FPGA_dclk is an output of the PFL and gets propagated to my top level wrapper output port. The FPGA_dclk is used normally to configure the FPGA.

How to constrain FPGA_dclk? With an output delay corresponding to the input clock?

I used create_clock command at the input pin (in_clk), the tool should automatically generate the correct FPGA_dclk on the output.

The kit I received for max5 from you specified the following DCLK constraint :

set_output_delay -add_delay -max -clock [get_clocks {clkin_50}] 0.000 [get_ports {fpga_dclk}]
set_output_delay -add_delay -min -clock [get_clocks {clkin_50}] 0.000 [get_ports {fpga_dclk}]

It specified 0.000 output delay. 

Is this right?  No delay at all on the output DCLK?

I had a warning "Min rise delay is equal to max rise delay", if use 0.000

So I used :

create_clock -name {clk} -period 100.000 -waveform { 0.000 50.000 } [get_ports {in_clk}]

# Create the associated virtual input clock
create_clock -name {clk_virt} -period 100.000 -waveform { 0.000 50.000 }

set_output_delay -clock clk_virt \
-max 0.001 \
[get_ports fpga_dclk]

set_output_delay -clock clk_virt \
-min 0.000 \
[get_ports fpga_dclk]

But is this right ?  

Back to my original question. How do I properly constrain DCLK which is currently an output ? Using set_output_delay ? If yes, please comment on the above in bold. What -max (for setup) /   -min (for hold) values can I use?

Regards,

Kevin

[Knug]

Hi @JohnT_Intel 

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[JohnT_Intel]

Hi,

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