How to solve error message for 17044 using device Arria 10: 10AX027H434i3SG in Quartus 18.1. It is urgent issue!

[fxu001]

Hello,

When I do analyze and elaboration step, Quartus 18.1 gives following error message as following as:

Error (17044): Illegal connection on I/O input buffer primitive image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|adc_gpio_for_ddio:adc1_bank1_in|adc_gpio_for_ddio_altera_gpio_181_drjngqi:gpio_0|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[8].altera_gpio_bit_i|input_buffer.ibuf. Source I/O pin in1Adc1Bank1FrameClk drives out to destinations other than the specified I/O input buffer primitive. Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.

I can't find anything wrong in the this IO connection. DO you have any suggestion?

When I remove the JESD204B IP, the problem is gone. DO you have any suggestion?

Thanks,

-Fred

Notes. I found the issue. Just add buffer because the error message indicated as "XXdrives out to destinations other than the specified I/O input buffer primitive"

[YuanLi_S_Intel]

Hi Fred, I am glad that the issue has already solved. Any more help needed? Regards, YL

[fxu001]

Hi YL, Thank you so much for your quickly response. First I thought the problem solved, but later on the issue came out again. Would you think there is a setting to cause this issue? Could you image that any file that might cause this issue. From my understand from the EDA tool behavior, it seems some setting issue, but I don't which one should be suspected? Thanks, -Fred

[fxu001]

Error (17044): Illegal connection on I/O input buffer primitive image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|adc_gpio5_for_ddio:adc1_bank1_in|adc_gpio5_for_ddio_altera_gpio_181_vcridrq:gpio_0|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[4].altera_gpio_bit_i|input_buffer.ibuf. Source I/O pin in1Adc1Bank0FrameClk drives out to destinations other than the specified I/O input buffer primitive. Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.

[YuanLi_S_Intel]

Hi Fred Xu,

This error indicates that the IP is not connecting correctly. May i know what IP you are using?

Regards,

YL

[fxu001]

YL, Oh, it is GPIO. I will try to narrow down the problem. Thanks, -Fred

[fxu001]

Hi YL, I think I found root cause. Basically Altera GPIO has two requirements: 1. It cannot drive two GPIO pins in the ddio mode. 2. it needs to directly drive from iBUF. The experiment and implement are both successful, and I am doing the integration with other modules which it should be okay now since I can use output to drive another fifo if I need. Please close this case. Thanks, -Fred