FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6400 Discussions

How to write to EPCS memory without disrupting code execution for DE0-Nano board ?


Hi all,

Currently I'm writing my program on DE0-Nano board, which contains an EPCS64 flash memory. My purpose is to save some information of the previous execution of the program, and I have an idea to write to the EPCS64 flash memory and at the beginning of my program, I read it back to get the information. However, I'm afraid that the same memory controller is shared between code and data memory. How could I write to the data memory without disrupting the code execution which executes the .jic file ? 

Also, as far as I've read, when I'm using the Quartus Prime Programmer tools to load the .jic file to the EPCS memory, it will erase the previous content. So how can I download the .jic file in this case ?

Thank you. 

0 Kudos
3 Replies

Hi ThangND,

May I know do have the .sof file? In the case if you have the .sof file, you can Launch Quartus Prime software and open your project.

Go to the "Processing" menu and select "Convert Programming Files" option.

In the "Convert Programming Files" window, click on "Add" button to add the .sof file to the list of files to be converted.

In the "Output file format" section, select "Jam STAPL Indirect Configuration (.jic)" as the output file format.

Configure any other settings as needed, such as the location and name of the output .jic file.

Click on the "Generate" button to generate the .jic file.

The .jic file will be generated in the specified location, and you can use this file to program the EPCS memory on your DE0-Nano board using a programmer, such as a USB-Blaster or other compatible programming tool.



0 Kudos

Please be advised that due to the absence of a response from you regarding the previous notification we provided, we will be transitioning this thread to community support. If you have any new questions or concerns, we kindly suggest opening a new thread to receive assistance from Intel experts. However, if you do not have any further inquiries, the community users will be available to assist you on this thread. Thank you for your understanding

0 Kudos
Valued Contributor III

the question involves a misunderstanding. FPGA configuration (and, if present, embedded processor code) stored in EPCS memory is not executed in user mode, it's loaded to FPGA internal memory after power on reset. EPCS memory can be read and written in user mode, e.g. through ASMI Parallel IP core.

Secondly, Quartus programmer only erases or overwrites the flash sectors specified in .jic file, unless you perform an intentional full erase operation.


0 Kudos