I'd like to try an Example Design for Avalon-MM Slave. Which one would you recommend to try with?

[ldm_as]

I'd like to try an Example Design for Avalon-MM Slave. Which one would you recommend to try with?

[Fawaz_Al-Jubori]

Hello,

May I know which IP are you referring to?

Avalon-MM Slave could be any IP. Furthermore, which FPGA board are you using?

Thanks

[ldm_as]

Actually I use an EVB for Arria-10. As for the Avalon interface, I'm writing a custom module, which should have an Avalon-MM Slave Interface. So, I'd like to run some Example Design in order to see its behavioral.

[Fawaz_Al-Jubori]

Hello,

You can run it either by simulation, or by real-time on board.

I would recommend using Nios II as a processor and connect your custom component to it. With a simple C application, you can test this custom component.

Please refer to this tutorial:

ftp://ftp.intel.com/Pub/fpgaup/pub/Intel_Material/13.1/Tutorials/Making_Qsys_Components.pdf

Thanks

[ldm_as]

Actually I wanted to see a Verilog/VHDL code, which implements a Slave Avalon-MM interface. This interface should support different latency of transactions (latency 0, 1, ...)

[Fawaz_Al-Jubori]

Hello,

You can export the custom component ports to the top level verilog file. Next, you can connect it to your verilog logic and test your design. Furthermore, you can add signaltap to trace the signals while running on board.

Unfortunately we dont have such a design.

Thanks