I have downloaded HDLC IP from opencores which is having front side bus as wishbone, I am using CYCLONE 4 FPGA with NIOS II processor. I want to interface HDLC IP to NIOS processor(AVALON BUS) please explain how to interface.

[KeenYewL_Intel]

Hi there, i believe this is a 3rd party IP from Intel PSG design partner. I would like to suggest perhaps you could refer to this link to contact the design house directly to get the info that you need.

https://www.intel.com/content/www/us/en/programmable/solutions/partners/partner-profile/digital-core-design/ip/dhdlc---hdlc-sdlc-controller.html