FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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I have downloaded HDLC IP from opencores which is having front side bus as wishbone, I am using CYCLONE 4 FPGA with NIOS II processor. I want to interface HDLC IP to NIOS processor(AVALON BUS) please explain how to interface.

scp001
Beginner
‎02-05-2020 06:14 AM
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KeenYewL_Intel
Moderator
‎02-06-2020 02:24 AM
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Hi there, i believe this is a 3rd party IP from Intel PSG design partner. I would like to suggest perhaps you could refer to this link to contact the design house directly to get the info that you need.

https://www.intel.com/content/www/us/en/programmable/solutions/partners/partner-profile/digital-core-design/ip/dhdlc---hdlc-sdlc-controller.html

 

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