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I2C Slave to Avalon MM Master bridge IP - Consecutive Write problem from odd addresses

Nikolay_Rognlien
New Contributor I
309 Views

We have a Qsys system with an I2C Slave to Avalon MM Master bridge IP connected as master to an On-Chip RAM.

 

When writing consecutive bytes to to the I2C Slave of the "I2C Slave to Avalon MM Master bridge IP" with a start address other than 32bit boundary(like 0x01, 0x02 or 0x03) the transaction is split up on the Avl MM side and two of the data bytes are used as address bytes in the next Avl MM write.

 

Writing with start address of 0x00 or 0x04 works fine.

 

Example:

 

Starting from i2c address 0x5, writing 8 bytes. Data in first byte is 1 and the value is incremented for each write operation. Expected output would be:

Adr

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

Data

1

2

3

4

5

6

7

8

 

But reading from the same address gives:

Adr

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

Data

1

2

3

0

0

0

0

0

 

It seems that the data for the fourth and fifth write operation somehow ends up in the i2c address. Reading 16 bytes from i2c address 0x400 gives:

Adr

0x400

0x401

0x402

0x403

0x404

0x405

0x406

0x407

0x408

0x409

0x40A

0x40B

0x40C

0x40D

0x40E

0x40F

Data

0

0

0

0

0

6

7

8

0

0

0

0

0

0

0

0

 

 

Doing the same write operation as above, but with a starting data value of 2.

 

Reading from address 0x5:

Adr

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

Data

2

3

4

0

0

0

0

0

 

And this time the rest of the data ends up in 0x506:

Adr

0x500

0x501

0x502

0x503

0x504

0x505

0x506

0x507

0x508

0x509

0x50A

0x50B

0x50C

0x50D

0x50E

0x50F

Data

0

0

0

0

0

0

7

8

9

0

0

0

0

0

0

0

 

This is how the signals look on the external I2C Slave SCL and SDA pins for a consecutive write starting at address 0x05:

 

Nikolay_Rognlien_1-1614950594683.png

Any ideas what may be wrong?

Is it a problem with the IP?

 

0 Kudos
1 Reply
SyafieqS
Moderator
218 Views

Hi Nikolay,


Any update on the issue?


Reply