IOPLL output clock issue Stratix10

[anat]

Hi Team,

I configured iopll IP for three output clocks, (outclk0)100MHz, (outclk1)200MHz and (outclk2)600MHz.  Ref clock is 100MHz.
I see duty cycle variation in the generated clock of 200MHz from iopll. I'm capturing the clocks using signal tap analyzer at a frequncy of 600MHz, genrated by same iopll.
Why the duty cycle is varying from 50%?

Clock waveform

IOPLL Settings

[sstrell]

You're not going to be able to see accurate sampling for a signal that fast.  Rely on the timing analyzer to verify your clocks, not Signal Tap, or output to a pin and view on a scope.  Signal Tap is for functional debug of data signals, not analyzing clocks.

[RichardTanSY_Altera]

SignalTap uses a clock to capture the data, so it's dependent on that clock rate. For logic, you want it to be the same clock that drives the logic you're tapping, as you need to synchronously tap it. For probing a clock, I'm not sure exactly what you're hoping to see. Normally people have the clock drive a counter and then just sample that with another clock, to calculate X transitions happened in Y time.  

Regards,

Richard Tan

[RichardTanSY_Altera]

Hi OP,

Dropping a note to ask if my last reply was helpful to you.

Do you need any further assistance from my side?

Regards,

Richard Tan

[RichardTanSY_Altera]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

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