IP Core Altera ALTPLL

[Altera_Forum]

I have a problem with the IP Core ALTPLL. I created the IP Core and I gave input to a PLL clock of 48 MHz to obtain an output clock of 96 MHz. When I simulate the output of the PLL I get that for the first six clock cycles at 48 MHz to 96 MHz output consists of xxxx. As you can eliminate this delay of six clock cycles and the x output?

[Altera_Forum]

I don't think you can remove those. This simulates the fact that the pll needs time to lock on the input clock before the output is valid. The pll has a "locked" output, and you should keep your design in reset as long as the "locked" signal isn't 1. When the pll locks, the locked signal is asserted and the output clock is valid.

[Altera_Forum]

thanks for the reply