IP Core compile error

[Michael_B_Intel]

Hello,

I'm using ATX PLL, PHY IP and IOPLL IP for a proof of concept of a transceiver project.

The IP core was successful in generation without any errors/warnings.

My VHDL files are without any compile errors.

Now in compilation I only receive errors in all the *.ip files.

Error(13224): Verilog HDL or VHDL error at h_tile_phy.ip(1991): illegal identifier : '_hw'

Error(13224): Verilog HDL or VHDL error at h_tile_phy.ip(2262): literal 8000000000 exceeds maximum integer value

Error(13224): Verilog HDL or VHDL error at h_tile_phy.ip(3677): literal 288230376151711743 exceeds maximum integer value

...

and further:

Error(13806): VHDL syntax error at atx_pll.ip(1) near text <

Error(17578): VHDL error at atx_pll.ip(1011): literal 8000000000 exceeds maximum integer value

..

and again:

Error(13806): VHDL syntax error at pll.ip(1) near text <

Error(13927): VHDL syntax error at pll.ip(3982): _sortIndex is an illegal identifier in VHDL

​So as I expect there should be errors in generation if there is something wrong and NOT in the compilation of IP components.

I'm using Quartus Prime Pro 19.1 for an Arria 10 GX DevBoard.

Best regards,

 Michael

[Deshi_Intel · Accepted solution]

HI Michael, Is this the Quartus synthesis compilation error ? I can help take a look on the error message if you can attached your quartus design archived QAR. You can also try start build new Quartus project from scratch and see whether the issue still persist or not. Sometime the IP database files may get corrupted and caused error. Thanks. Regards, dlim

[Michael_B_Intel]

Hi dlim,

Thanks for your answer and your hint!

I created a new project where the issues did not come anymore.

After that I've compared both .qsf files to identify the root cause.

Root cause was the *.ip files where listed as 'VHDL/VERILOG file' and not as IP core file.

Thanks a lot!

This topic can be closed :)

Best regards,

Michael