FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6024 Discussions

Illegal Connection with GPIO Intel® FPGA IP output buffer.

JHaye4
New Contributor I
544 Views

I am using the GPIO Intel® FPGA IP core to connect a Intel FPGA Avalon I2C (Master) Core to the pins of my FPGA.

When I connect the "dout" port of the buffer in bidirectional mode to my core logic I get the following error:
Error(17046): Illegal connection found on I/O output buffer primitive i_od_bi_buf|gpio_0|core|i_loop[1].altera_gpio_bit_i|output_buffer.obuf to i_od_bi_buf|gpio_0|core|i_loop[1].altera_gpio_bit_i|input_buffer.ibuf. The IO output buffer should only drive out to a top-level pin.
If I leave this pin "open" the error goes away; however, this is not suitable as I need to feed the dout port into my I2C master.

I am following the guidance in both user guides yet cannot get this to work.
I'm using Quartus Pro 19.4.0 targetting a Cyclone 10 GX device.

0 Kudos
3 Replies
JHaye4
New Contributor I
541 Views

Resolved by not being silly and connecting ports correct way round.

JHaye4
New Contributor I
525 Views

Not resolved, still having the same warning. Cannot connect bidirectional IO buffer without generating errors.

 

sstrell
Honored Contributor III
500 Views

How have you set up your pin assignments in the Pin Planner?

Reply