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Interfacing with Altera-MM Salve of UniPHY DDR2 controller

Altera_Forum
Honored Contributor II
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Hi to all.... 

This is my first post in this forum and my english is not quite good... 

 

 

I have some problem with a UniPHY interface generated trought Megawizard (Quartus II 13.0 with a Stratix IV device) for the interface with a DDR2 memory. 

 

 

As I read in the documentation and in this forum I have in the user side an Avalon-MM Slave interface so I used the Avalon specification chapter 3. 

 

 

I have some doubts  

 

  • respect the sincronizzatio of the avalon interface: The signal ( in particular the avl_ready = not(waitrequest)) changes on the clock edge so if I use a statement like @(posedge clk) I read the state only on the following clock edge cause two read request. 

 

 

 

 

  • Wher i can find the properties of the generated Avalon-MM interface listed in the table 3-2 of the Avalon Specification? 

 

 

 

First I must write data in the interface otherwise when I try to read the interface return "x" data. 

 

 

When I use a write burst size of "1" and make a read request (also with burst size 1) the interface return to two valid data. 

Figure 1-1 

 

 

When I use a write burst size of "1" and make a read request with burst size =3 the interface return 3 valid data but the first two are egual. 

 

 

Figure1-3 

 

 

 

 

 

 

Otherwise when I use a write burst size different from 1 the following read request are ignored. 

figure 21 

figure 2-3 

 

 

This is the question... More Important is to find the properties of the interface because I'm not sure on the addressing and data size of the Avalon-MM interface. 

 

 

Thanks to all! 

 

Edit: Sorry but I can't upload image. Return an invalide file. The image are a .png of size less then 100kb. Suggestion?
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