FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6670 讨论

Is clock neede in DSP builder design?

Altera_Forum
名誉分销商 II
1,401 次查看

Is it necessary to add a clock in DSP builder design?

0 项奖励
6 回复数
Altera_Forum
名誉分销商 II
564 次查看

I'm not 100% certain on on the clock is essential, but if you don't add a clock to a DSP builder design then when you compile it you will have no clock definition (as required in the .sdc file) and it will not try to acheive a required Fmax. Also, I think it will need the clock in order to simulate the design in Simulink.

0 项奖励
Altera_Forum
名誉分销商 II
564 次查看

Thanx but i am talking about desinging with DSP biulder not with Simulink....

0 项奖励
Altera_Forum
名誉分销商 II
564 次查看

DSP Builder is an add-on for Simulink in MATLAB...

0 项奖励
Altera_Forum
名誉分销商 II
564 次查看

You need to use a clock block to derive the clock rate, else it will just assume it is running at 50 Mhz. You wont find any clock pin in the design, but after you have compile it, from the top level VHDL file, you will notice there is a clock input pin that required to connect to a clock source from hardware.

0 项奖励
Altera_Forum
名誉分销商 II
564 次查看

Using the DSP Builder Standard blockset you should add the Clock Block. Using DSP Builder Advanced blockset, clock settings are on the Signals block.

0 项奖励
Altera_Forum
名誉分销商 II
564 次查看

Yes, those blocks are needed to configure the clock setting in DSP builder design.

0 项奖励
回复