FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6365 Discussions

Is it possible to connect the output of a Cyclone V dynamic delay chain to an ALTLVDS_RX SERDES receiver?

AFien
Beginner
‎11-16-2019 07:42 PM
543 Views

I am using the ALTIOBUF IP core to control the dynamic delay chain. I was hoping to use the delay chain to fine-tune a DDR LVDS interface.

 

Thanks!

0 Kudos

Link Copied

1 Reply
Rahul_S_Intel1
Employee
‎11-21-2019 11:07 AM
308 Views

Hi ,

In Cyclone V , the delay chain did not have any connection to Alt LVDS .

 

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.