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Altera_Forum
Honored Contributor I
708 Views

Is video packet from VIP core always contain full frame?

Hi, 

I have implemented my custom IP core compatible with VIP Avalon ST-interface. I receive correct control packet and then I'm waiting for video packet with whole video frame data, but I receive about 1000 pixels and got EOP signal. So is VIP Avalon ST allow to fraction video frame data into several packets? 

Thanks!
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6 Replies
Altera_Forum
Honored Contributor I
10 Views

In general the answer is no. 

 

If you have e.g. a Test-Pattern-Generator, you will ever get a full video-frame. Could you please give more detail about your setup and configuration. 

 

If you have a Clocke-Video-Input, it all depends on the Input... 

 

So please give a short block-diagramm or similar as example for your setup. 

 

Kind regards
Altera_Forum
Honored Contributor I
10 Views

Thanks for reply! 

I have following video path: 

Clocked Video Input(progressive, 1280x1024) -> clipper-> gamma corrector -> filter -> st-splitter(out1) -> frame buffer -> a lot of cores for convert to PAL output. 

st-splitter(out2) -> fifo -> scaler -> my custom JPEG encoder. 

I found that invalid frame comes during start up, but not sure it comes just one time... 

I have found "Discard invalid frames/fields" parameter in Frame Buffer, it seems it all I need, but it is not reasonable to occupy memory bandwidth for dropping invalid frames only. My encoder is faster than my video source, so no additional frame rate conversion is needed. 

Thanks!
Altera_Forum
Honored Contributor I
10 Views

Sorry, but you probably need to use simulation or SignalTap to figure out where things fall apart. The first thing to double check is that the control packet you're receiving (width,height) actually does say >1000 pixels you're receiving. 

 

Then the second thing to check would be what's going in and out of the Frame Buffer and the FIFO, as that looks the most likely place for an overrun to occur.
Altera_Forum
Honored Contributor I
10 Views

Hi Ted, 

I'm using SignalTap. Control packet is OK, width and height is correct. 

I will investigate FIFO input and output, thanks. 

Thanks for answer!
Altera_Forum
Honored Contributor I
10 Views

As Ted and I said before, the Problem seems to be the Clocked-Video-Input. Maybe it takes some time from startup of the FPGA to a stable input video?!

Altera_Forum
Honored Contributor I
10 Views

I'm waiting for "video stable" flag during startup. Yes, I think you right - my image sensor can have some synchronization problems, I have long cable from sensor to PCB. I think it will good practice to implement protection from invalid frames inside my IP core. Thanks!

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