FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

I2C Woes, Opencore and Terasic

Some problem to integrate HDL Import block in Advanced design

The problem of VCI.

SAA7113+VIP need help

SOPC Custom components: memory custom component

Looking for advice on large FIFO implementation

VIP FIR Filter 2D

Q10.1, cyclone IV and DDR2 altmemphy problem

serdes with on 8b/10b

Help with PCIe interrupts

PIPE Interface

help: the DDR2 controller works incorrectly

ALT2GXB Help................

State Machine to Drive DDR Controller works but does not.

Error running emi_ddr2_aiigx with Q10.0sp1 on Dev. Kit Arria II GX EP2AGX125EF35

Featured Content

problem to use F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*

How to switch the HDMI PHY reference clock to the HDMI Rx TMDS clock ?

Arria 10 PCIe Retraining with LMI with Configuration Space Bypass Enabled

EPCQ16ASI8N marking

RMA for EP4CGX110DF27I7N

5CGTFD5C5F23C7N